Design of Parallel Self-Timed Adder

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Adders being core building blocks in different VLSI circuits like microprocessors, ALU’s etc. performance of adder circuit highly affects the overall capability of the system. In this paper we present the design and performance of Parallel Self-Timed Adder. It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. The proposed work mainly aimed at minimizing the number of transistors and estimation of various parameters viz., area, power, delay for PASTA. We have also designed 4 bit PASTA as an example of proposed approach. Simulations have been performed using MICROWIND 3.1software and DSCH tool in 45nm CMOS technology that verify the practicality and superiority of the proposed approach over existing asynchronous adders.